The evolution of the electronics industry in recent years has resulted in a steady decrease of integrated circuit feature sizes. With the introduction of the 256K chip and research on the 512K chip in progress, feature sizes are shrinking to such a degree that many of the traditional semiconductor progressing techniques are no longer adequate. Until recently, doped polysilicon has been used extensively as a conductor for gate interconnects on metal-oxide semiconductor (MOS) devices. Doped polysilicon was chosen because it can withstand subsequent high temperature processing steps and because it has electrical properties, such as a bulk resistivity of about 1,000 .mu..OMEGA.-cm, which are desirable. As conductor line widths are reduced to below 2.mu., however, the resistance of polysilicon conductive lines is large enough to degrade the high speed performance of devices. Thus, with minimum feature sizes of 1.mu. or less, the electronics industry has looked to refractory metal silicides as a solution to gate interconnect problems in high density chip production.
Refractory metal silicides are now being used in place of polysilicon or in addition to polysilicon (as a two layer polysilicon-silicide conductor sometimes referred to as a polycide). Refractory metal silicides have very low bulk resistivities (approx. 15-100 .mu..OMEGA.-cm), can withstand temperatures in excess of 1,000.degree. C. and, in general, do not oxidize easily. The silicides commonly associated with the formation of gate interconnects are titanium silicide (TiSi.sub.2), tungsten silicide (WSi.sub.2), molybdenum silicide (MoSi.sub.2) and tantalum silicide (TaSi.sub.2).
Currently, a variety of methods are employed to produce conductive silicide coatings. They include sputtering or cosputtering techniques, evaporation or coevaporation processes, chemical vapor deposition processes requiring high substrate temperature (pre- or post-deposition), and plasma induced chemical vapor deposition. For a detailed discussion of many of these methods see Murarka, Refractory Silicides for VSLI Production, Academic Press, 1983, pp. 115-131.
Sputtering techniques employ target materials which are bombarded by energized ions to free atoms of the materials for deposition onto a substrate. The techniques include sputtering of a metal on silicon or polysilicon or simultaneously sputtering from two targets (cosputtering). Both techniques employ radio frequency (RF, plasma) or direct current (DC) magnetron sputtering for silicide formation.
DC magnetron sputtering is of limited use because it requires that the target material be a conductor. Thus, when a metal target and a silicon target are employed as in a cosputtering process, the silicon target must be doped to make it a good conductor. Consequently, the resultant silicide layer may include an unwanted dopant.
Sputtering techniques cause gas entrapment and/or contamination to occur in the deposited layer. The bombarding ions are gas ions which become entrapped in the silicide layer. These gas ions can chemically contaminate the layer if the gas contains a chemically reactive impurity.
Silicide coatings produced by the physical deposition process of sputtering or cosputtering are invariably amorphous. These amorphous coatings have a high resistivity as deposited and must be annealed at 900.degree. C.-1,100.degree. C. for 0.5-1.0 hr. to produce high quality coatings of low resistivity. A high temperature anneal (greater than about 1,000.degree. C.) can create warpage of the silicon chip which makes subsequent lithography difficult. Additionally, at 1,000.degree. C. or higher, dopant diffusion becomes a significant factor and can result in unwanted alteration of dopant profiles.
Poor step coverage is another drawback associated with sputtering or cosputtering. Because the topography of the wafer surface is varied, good step coverage is necessary to avoid degradation or failure of the device. Sputtered and cosputtered layers exhibit poor step coverage as compared to other prior art processes. The result of poor step coverage is localized thin spots which can produce overheating, electromigration of the conductor and, consequently, premature failure of the device.
Evaporation techniques include evaporation of metal on silicon or polysilicon and coevaporation of metal and silicon on silicon, polysilicon or oxides. The techniques use heat (resistive, inductive (RF), electron bombardment or laser) to vaporize the elements which are deposited on the substrate surface. One problem specifically associated with coevaporation is consistency of the silicide composition from run to run. In addition, electron guns, commonly used as the heat source for refractory metal silicide formation, cause radiation damage to the substrate.
Regardless of the specific evaporation process employed, formation of a highly conductive silicide layer requires post deposition processing at temperatures of 900.degree. C.-1,100.degree. C. As with sputtering processes, high temperature (greater than 1000.degree. C.) post deposition processing steps can cause substrate warpage and significant dopant diffusion. Furthermore, step coverage by evaporation techniques is generally no better than the coverage produced by sputtering techniques.
Chemical vapor deposition (CVD) of silicides requires a chemical reaction of materials in the vapor phase or a reaction which occurs on the substrate surface. Chemical vapor deposition requires a high substrate temperature to produce a conductive coating (1,000.degree. C.-1,100.degree. C. for TiSi.sub.2, see Wahl et al., "The CVD Deposition of Ti-Si Containing Coatings on Ni-Base Superalloys," Proceedings of the Eighth International Conference on Chemical Vapor Deposition, Electrochemical Society, Pennington, N.J., 1981, pp. 685-98. These high temperature processing requirements induce the same problems which occur during sputtering and evaporation post deposition treatments. However, unlike the step coverage problems associated with sputtering or evaporation of silicide films, CVD films exhibit good step coverage.
Cold wall, low pressure CVD processes have developed quite recently as an alternative to high substrate temperature processes. Examples of this process are described in "Cold Wall, Low Pressure CVD Reactor" Solid State Technology," November 1983, pp. 63-4 and Brors et al., "Properties of Low Pressure CVD Tungsten Silicide as Related to IC Processing Requirements," Solid State Technology, Vol. 26, April 1983, pp. 183-6. The product, produced on a substrate heated to a low temperature, is either microcrystalline or amorphous. In order to produce a conductive layer, however, a high temperature anneal (1,000.degree. C.-1,100.degree. C.) is required for either process. Again, this high temperature post deposition treatment can cause substrate warpage and unwanted dopant profile changes.
A plasma induced CVD process is briefly disclosed in "Plasma Titanium-Silicide--Path of Least Resistance," Solid State Technology, January 1984, p. 37. Although this process employs somewhat lower processing temperatures, a principal drawback of this process is the distinct possibility of radiation damage to the substrate.
In an effort to reduce the effects of high temperature processing, lasers and electron or ion beams are used to anneal the layers. These heat treatment processes localize the heat and are needed only for a very short time to produce the conductive layer. See, for example, Murarka, supra, p. 128.
Most recently, laser induced chemical vapor deposition (LCVD) has been used to produce semiconducting, insulating and conductive (metal) coatings. The laser induced reactions cause the gaseous constituents to react and produce a coating on the substrate. References discussing the production of Si semiconductive layers, oxide and nitride insulating layers and conductive metal layers include: U.S. Pat. No. 4,227,907; U.S. Pat. No. 4,270,997; U.S. Pat. No. 4,260,649; U.S. Pat. No. 4,324,854; Bilenchi et al., "Laser-Enhanced Chemical Vapor Deposition of Silicon," Proceedings of the Eighth International Conference on Chemical Vapor Deposition," Electrochemical Society, Pennington, N.J., 1981, pp. 275-83; Gattuso et al., "IR laser-Induced Deposition of Silicon Thin Films," Mat. Res. Soc. Proc., Vol. 17, 1983, pp. 215-22; Allen et al., "Summary Abstract: Properties of Several Types of Films Deposited by Laser CVD," Vac. Sci. Technol., March 1983; and Meunier et al., "Hydrogenated Amorphous Silicon Produced by Laser Induced Chemical Vapor Deposition of Silane," Appl. Phys. Lett. 43(3), 1 August 1983, pp. 273-5. In addition, a comprehensive list of documented laser induced reactions is disclosed in Steinfeld, "Laser-Induced Chemical Reactions: Survey of the Literature, 1965-1979," Plenum: New York, 1981, pp. 243-67.
Until now, despite the recognition in the electronics industry that metal silicides are instrumental in VLSI and VVLSI production and notwithstanding the volumes of literature to date discussing the methods of forming coatings, production of satisfactory metal silicide coatings by a process which does not require high temperature processing steps to achieve a sound highly conductive layer has not been possible.
We have discovered a novel process for the production of conductive titanium silicide-containing films and composites. The process eliminates the high temperature processing steps normally required to form conductive titanium silicide-containing films. The process preferably employees a laser to induce chemical vapor deposition of a polycrystalline conductive titanium silicide-containing film on a substrate. The conductive films have an easily controllable composition and, when forming composites, the composites exhibit excellent step coverage. The novel process produces films and composites which are ideally suited for integrated circuit production.